(PDF) Fine pitch stencil printing of Sn/Pb and lead free solders for flip chip technology - DOKUMEN.TIPS (2024)

IEEE TRANSACTIONS ON COMPONENTS, PACKAGING, AND MANUFACTURING TECHNOLOGY—PART C, VOL. 21, NO. 1, JANUARY 1998 41

Fine Pitch Stencil Printing of Sn/Pb and LeadFree Solders for Flip Chip Technology

Joachim Kloeser,Member, IEEE,Katrin Heinricht, Kai Kutzner, Erik Jung,Andreas Ostmann, and Herbert Reichl,Senior Member, IEEE

Abstract—This paper presents a flip chip technology based onan electroless Ni/Au bumping process which has been developedby IZM/TUB. Nickel bumps offer a surface with very good suit-ability for flip chip soldering. In the following, an interconnectionmethod is described which uses ultra fine pitch stencil printingof solder paste on wafers, ceramic, and organic substrates.

The eutectic Pb/Sn solder alloy is by far the most commonlyused solder in industry. Facing the ecological challenge andfederal legislation the paste suppliers are developing lead freesolder pastes. Due to the fact that the variety of solder pastes isstill growing it is necessary to find an ideal alloy for a specificapplication. Therefore, in comparison to eutectic Sn/Pb solderdifferent alloys, e.g., Bi/Sn, Sn/Bi/Cu, Sn/Ag, Sn/Cu, Au/Sn areinvestigated in this paper.

In the first part of this paper a low cost flip chip technol-ogy based on chemical Ni/Au bumping and solder printing ispresented. For this the basic process steps and key aspects aredescribed in detail. The experimental results of an ultra fine pitchtechnique on wafers and on substrates are shown as well.

The second part of this paper presents a comparison of theproperties of different solder pastes concerning the usability forflip chip technology. For this, flip chip soldering using dies withNi/Au bumps was performed on ceramic and FR-4 substrates.The quality of the flip chip joints were investigated by metallur-gical cross sections and electrical and mechanical measurements.Finally, the reliability results of these joints after thermal cyclingare presented.

Index Terms—Alternative solders, high temperature applica-tions, low cost, reliability, stencil printing.

I. INTRODUCTION

FLIP chip technology has obtained an increased levelof acceptance for many different applications. Over the

next few years flip chip technology is expected to becomewidespread reality in automotive, consumer, and telecommu-nication applications [1]. A breakthrough, however, will onlybe reached once the use of flip chip promises cost reduction,increased package density, and reliability improvement.

A key issue for this will be the implementation of low costbumping processes. Chemical bumping processes based onelectroless nickel plating have been presented from several

Manuscript revised October 17, 1997. This work was supported by theGerman Federal Ministry for Research and Development and the EuropeanCommission (European Project ECOMOD 16 SV 034).

J. Kloesner, K. Heinricht, K. Kutzner, E. Jung, and H. Reichl are with theDepartment of Reliability of Chip-Interconnection Technology and MultichipModules, Fraunhofer Institute FhG/IZM-Berlin, Berlin D-13355, Germany(email: [emailprotected]).

A. Ostmann is with the Microperipheric Research Centre, Technical Uni-versity of Berlin, Berlin, Germany.

Publisher Item Identifier S 1083-4400(98)02865-4.

authors [2]–[7] as a low-cost alternative. According to theeconomical bumping technique the industry needs low cost andhigh density substrates for use with flip chip devices. For thislow temperature cofired ceramic substrates (LTCC) and rigidor flexible laminates have the most promising potential. Inthe automotive under-the-hood applications for example LTCCsubstrates are used at the moment but for further cost reductionorganic laminates are under development as well [8].

The development of underfill materials which compensatethe mismatch in the coefficient of thermal expansion (CTE)between the chip and the substrate plays a key role for theapplicability of flip chip technology especially on low costFR-4 boards [9], [10]. It could be also demonstrated thatencapsulation on ceramic substrates leads to a significantimprovement in the life time of these devices [11]–[13].

Furthermore, the increasing interest in cost effective flipchip technologies leads to the development of various flexiblemethods for the deposition of solders and adhesives on chip orsubstrate. In addition many suppliers improved the propertiesof solder materials, solder pastes, solder balls, solder wires,and adhesives [14].

In this paper, the studies are focused to processes for stencilprinting solder paste. The conventional printing methods andmaterials are not suitable for applications with fine pitchstructures. To achieve reproducible and hom*ogeneous solderdeposits the process techniques for fine pitch printing requirean improvement of the physical properties of solder paste,of the stencil materials and stencil processing technologies aswell as the printing equipment. Using solder printing for ultrafine pitch applications solder pastes with very small particlesizes, a nitrogen atmosphere, and well controlled temperatureprofile of the reflow furnace is required.

Environmental and toxicity concerns related to the use oflead have initiated the search of acceptable, alternative joiningmaterials for electronic assembly [15]. Besides the ecologicalaspects for flip chip applications the need is to developnew solders that have similar processing characteristics andusage cost to Pb/Sn solders, but are lead free and haveimproved mechanical properties and microstructural stability.Nevertheless, one of the important goals for the developmentof lead free solders for flip chip technology is to increasethe reliability of the flip chip joints in order to renounce theunderfill process step. In this context flip chip assembly usingdifferent solders was performed on substrates with differentCTE values. The reliability was investigated by thermo cycling( 55 C/ 125 C).

1083–4400/98$10.00 1998 IEEE

42 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING, AND MANUFACTURING TECHNOLOGY—PART C, VOL. 21, NO. 1, JANUARY 1998

Fig. 1. Basic processes and materials for low cost flip chip assemblytechnology.

Fig. 2. Ni/Au bump.

The first reliability investigations of the lead free soldersfor flip chip applications are focused to extract potential andpromising candidates for further studies.

In the following, the basic process steps required for the de-velopment of a cost effective and flexible flip chip technologyare described in detail. Fig. 1 shows the elements of an in-lineflip chip assembly process capable of high volume production.

II. ELECTROLESSNICKEL-GOLD BUMPING

Ni bumps (Fig. 2) fulfil the following function. They protectthe Al and act as adhesion layer and a diffusion barrier andguarantee a stable and reliable contact to the Al bond pads.Besides this, which is mainly the function of an UBM, theNi can also offer a stand-off, e.g., for chip on glass (COG)assembly using anisotropic conductive films (ACF’s).

The electroless bumping process is wet-chemical and mask-less. Nearly all types of semiconductor wafers can be bumpedby this process (Fig. 3).

In the IZM bumping line up to now, more than 90 differenttypes of functional wafers have been bumped. Fig. 3 showschemically plated nickel bumps on a 6-in CMOS wafer.

A documented process control system is installed whichguarantees constant operation conditions. The quality of Ni/Aumetallization is monitored by optical microscopy, profilometermeasurements and shear tests.

A. Process Flow

First, in order to prevent Ni plating, the wafer backsidehas to be covered by a resist prior to the chemical bumping

Fig. 3. Ni/Au bumps on a CMOS wafer.

Fig. 4. Process flow of electroless Ni/Au bumping [16].

process. The next step is a treatment in an Al cleaner whichremoves oxide layers while the Al surface is micro-etched. Azincate solution is used for activating the Al surface. For theelectroless Ni plating a bath based on sodium hypophosphite isused. A final Au coating on the Ni is necessary to prevent oxi-dation and enables long-time solderability of bumps. StandardAu thickness is 0.05 m. The process flow is shown in Fig. 4.

B. Bump Characteristics

The minimal bump height is 1m to have a closed andvoidless Ni-layer. Because of the isotropic growth of thenickel, the maximal height is limited by the pad to padspacing. Bump height must not be larger than 1/2 pad spacing(plus 10 m for security) to avoid short circuits betweenneighboring pads by overgrowing Ni. A height of 5m isrecommended for FC soldering as it meets the requirementsof reliability and fast processing. The adhesion of the bumpson the Al pads is measured by the shear force that is required topush the bump horizontally off the pad. For the Ni/Au bumps,an adhesion of at least 100 MPa is achieved (i.e., 100 cN shearstrength for a 100 100 m pad). Thus, shear strength of thebumps depends on the pad size. A thin Au coating protects theNi from oxidising and keeps it solderable. It can be adjustedup to 0.25 m (standard is 0.05 m) to prevent any solderembrittlement. The uniformity of bump height is2% on 4-inwafers and 4% on 8-in wafers, which is sufficient for nearlyall types of applications. Data on the reliability of the Al/Niinterface has been published [17]. The characteristics of Ni/Aubumps are summarized in Table I.

KLOESER et al.: FINE PITCH STENCIL PRINTING OF SN/PB AND LEAD FREE SOLDERS 43

TABLE INi/Au BUMP SPECIFICATION

TABLE IIDESIGN RULES FOR Ni/Au BUMPING

C. Wafer Design Rules

Table II summarizes the design rules for the electrolessNi-deposition. Bond pad metal AlSi1%, AlSi1%Cu0.5%, andAlCu2% with a thickness of 1 m are acceptable. In particularcases also Al down to 0.5m is acceptable. There are no limitsto passivation thickness but the passivation must be free ofdefects. Cracks or pinholes are not acceptable. The scribe linehas to be almost insulating (a thin thermal oxide is sufficient).Metallized test structures or alignment marks are acceptable.

The pad spacing has to be at least 20m to prevent shortsby overgrowing Ni. Probe marks on the aluminum surfaceare not causing reliability or processing problems. The Niovergrows the Al deformed by probing. Probing after Ni/Auplating causes no damage of the bumps due to the hardness ofNi. Some wafers (e.g., memories or analog devices) have lasertrimming structures. Whether these structures are acceptabledepends on the used technology. A summary of the waferdesign rules is shown in Table II.

III. SOLDER PRINTING

For flip chip soldering a selective solder deposition onthe wafer or substrate is essential. The highest potential forlow cost flip chip assembly has the stencil printing of solderpaste. The printing technology is widely used, e.g., in SMTassembly. The challenge is to develop this technique toward a

flip chip suitable pitch of 200 m and below for mass volumeproduction.

The stencil printing process has many variables. Followingfactors must be taken into account to achieve high quality,precise and reproducible fine pitch solder paste printing [18]:

Operators training, awareness, authority;Environment temperature, humidity, dust;Methods snap-off, squeegee pressure; alignment;Materials solder paste, stencil, squeegee;Equipment printer, stencil holder.

For fine pitch printing in the past few years tools andprocesses have been improved. Efforts have been focusedon the development of soldering materials, especially solderpastes.

For flip chip applications the particle size of the solder pasteis one of the most important factors. Therefore some suppliersdeveloped pastes with hom*ogenous distribution of particlesand sizes smaller than 25m. Furthermore, at present differentalloys complementary to Sn/Pb are available, e.g., Au/Sn,Ag/Sn, Sn/Bi/Cu, Bi/Sn, Sn/Cu, and Indium based materials.

Depending on the application stencil printing of solderpastes can be performed on substrates and whole wafers. Thevolume and the height of the deposited solder depends on thethickness, the size of the openings of the applied stencil, andthe squeegee material.

A. Experimental Results

The printing was performed with a precision printer fromDEK (DEK 265) and we used a metal squeegee. The snap-off distance was set up 0 mm. Stencils with apertures madeby laser cutting, etching, or electroforming were investigated.The best results could be achieved using laser cut stencils fromSystronic. The stencil apertures were adapted to the specificapplication. The volume of the printed paste is determinedby the aperture diameter and the stencil thickness. Since theaperture size is limited due to the pitch, the stencil should be asthick as possible. On the other hand a high thickness to openingratio will increase the risk of paste sticking. The design ruleused in SMT, the stencil opening should be approximately 1.5times the thickness of the stencil is not evident for to flip chipgeometries. Therefore the selection of the appropriate stencilgeometry is essential for printing with high yield [14]. Fig. 5shows the influence of the aperture size on height of the bumpsafter reflow. The thickness of the stencil was constant (80m).The study of the optimal geometry and optimal ratio of aper-ture size to stencil thickness will be the subject of a paper pre-sented at the EUPAC’98 Conference in Nurenberg, Germany.

B. Stencil Printing on Substrates

Stencil printing was performed on ceramic and FR-4 sub-strates [14]. In this case chips with Ni/Au bumps can directlybe placed on the substrates without preceding solder reflow.Therefore the wet solder paste acts like a buffer to compensateslight inplanarities of solder deposits. The minimal pitch ofthe printed deposits was 200m. We applied solder pastefrom Multicore (Sn62RA90). The properties of this pasteare: solder alloy Sn/Pb/Ag-62/36/2, melting point 179C,

44 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING, AND MANUFACTURING TECHNOLOGY—PART C, VOL. 21, NO. 1, JANUARY 1998

(a) (b)

Fig. 5. Solder bumps on a wafer after reflow showing dependence on theaperture size of the stencil. Stencil thickness 80�m. Bump height: (a) 135�maperture size 210�m (circle) and (b) 85�m aperture size 130�m (circle).

Fig. 6. Process flow of solder bumping.

measured maximal particle size between 10–25m, no cleanflux S-FW 32 (RMA-type).

C. Stencil Printing on Wafers

The solder paste application on the Ni UBM is performedby a DEK 265 printer. Printing is performed on wafers from4–8 in using special carriers. The Ni UBM has a thickness of5 m. Thicker Ni will not increase total height of the solder.The final height of solder bumps depends only of the printedpaste volume. The solder paste is PbSn63 alloy with particlesizes from 15–25 m.

The solder paste is reflowed in a convection oven undernitrogen atmosphere. Flux residues are cleaned in a solventadapted to the used solder paste. The process steps can beseen in Fig. 6. Fig. 7 shows SEM photographs of a bump siteduring processing. Typical height of reflowed solder bumps is100 m at pitches down to 200m (see Fig. 8). Maximumpossible solder bump height is determined by the smallestpitch and bond pad layout of the wafer. The achieved bumpuniformity is 5 m on 4-in wafers. The distribution of bumpheights on a wafer is shown in Fig. 9. Specifications of solderbumps are summarized in Table III.

IV. PROPERTIES OF THEAPPLIED

SN/PB AND PB-FREE SOLDER ALLOYS

Lead tin solders are the most used joining materials for theinterconnection and packaging of modern electronics because

(a) (b)

(c) (d)

Fig. 7. SEM pictures of solder bumping steps: (a) bond pad in initial state,(b) with Ni/Au UBM, (c) with printed solder paste, and (d) after solder reflow.

TABLE IIISOLDER BUMP SPECIFICATIONS

Fig. 8. Solder bumps, height 95�m, pitch 300�m.

of their unique combination of low cost and convenientmaterial properties [19]. The global drive to replace the useof toxic lead metal and alloys in industrial applications hasfocused, in part, on the development of new Pb-free solderalloys. The eutectic Sn/Pb alloy is by far the most commonlyused solder in industry and a simple drop-in replacementalloy with substantially the same melting temperature is ingreat demand. For instance it is common practice in electronicpackaging to solder the various levels of the package withdifferent solders of different melting points so that the sol-

KLOESER et al.: FINE PITCH STENCIL PRINTING OF SN/PB AND LEAD FREE SOLDERS 45

TABLE IVAPPLIED SOLDER PASTES FOR STENCIL PRINTING

Fig. 9. Solder bump height distribution on a 4-in wafer.

dering of each successive level or step does not remelt thepreviously soldered joints. Furthermore an enhancement of themechanical properties of the alternative paste is an importantissue.

In theory many solders could replace or complement theeutectic solder in assembly technology. Several authors havealready published results of alternative solders [20]–[24]. Theinvestigations in this paper are focused to solders suitablefor flip chip technology. Table IV summarizes the appliedsolder pastes. Concerning the reflow temperature the Sn/Bi/Cupaste is a promising alternative to Sn/Pb alloys because ofits similar melting point and excellent mechanical properties.For high temperature applications eutectic Sn/Ag-, Sn/Cu-, andAu/Sn pastes are used. Eutectic Au/Sn is suitable for flux freesoldering. For low temperature applications a Bi/Sn alloy willbe a promising alternative.

V. FLIP CHIP BUMPING

Due to the different flux formulations of the various solderpastes, the metal content of the pastes differ. Especially, asexcept for the SnPb63/37 solder paste all other pastes were

TABLE VBUMP HEIGHTS WITH THE DIFFERENT SOLDER

PASTES (STENCIL THICKNESS: 80 �m)

not specifically designed for flip chip applications. Thus, asthey have nonoptimized particle distribution, they may varylargely in their metal content by volume and in their printingcharacteristics (e.g., rheological properties). This results indifferent bump heights after reflow when using the same stencilgeometry.

Table V gives the respective bump heigths obtained withthe different solder pastes (mean of 30 measurements).

This implies that the subsequent results must be carefullyanalyzed. The microstructural appearance of the bumps wasinvestigated using SEM. It was observed, that the SnPb- 63/37and BiSn 57/43 solder shows much coarser grain structuresthan do the SnCu-97/3 or SnAg-96.5/3.5. AuSn-80/20 andSnBiCu-90/9.5/0.5 show microstructures in between the fineness of the beforementioned alloys. Figs. 10–12 show therespective SEM images.

According to this fine grained morphology and accordingto the results of previous investigations, this should allow agreater shear resistance and an increased lifetime by greaterfatigue resistance [15]. Shear tests performed at different statesof thermal exposure (125C up to 1024 hrs) revealed that forflip chip bumps this general rule does not hold, as not onlythe bump material is tested and stressed but also all associatedinterfaces. Fig. 13 shows the respective graph of shear forces

46 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING, AND MANUFACTURING TECHNOLOGY—PART C, VOL. 21, NO. 1, JANUARY 1998

(a) (b)

Fig. 10. Flip chip bump solder (500�): (a) BiSn-53/47 and (b) Sn/Cu-97/3.

(a) (b)

Fig. 11. Flip chip bump solder (500�): (a) Sn/Pb-63/37 and (b)SnAg96.5/3.5.

(a) (b)

Fig. 12. Flip chip bump solder (500�): (a) Sn/Bi/Cu-90/9.5/0.5 and (b)Au/Sn-80/20.

for the different alloys. No major influence of thermal exposureto 125 C on the bump adhesion could be observed during thistest, although for the BiSn57/43 eutectic the test was quite nearto the melting point of 139C.

The AuSn80/20, as a high temperature solder was exposedto 150 C Here a slight degradation of the shear force dueto grain coarsening at the 150C exposure temperature wasobserved. However, no adverse influence on the flip chipreliability is expected.

VI. FLIP CHIP ASSEMBLY AND

PRELIMINARY RELIABILITY RESULTS

Fig. 14 shows the process flow chart for flip chip assemblyby printing solder paste on wafers or substrates. For the reflowprocess of fine pitch solder pastes a nitrogen atmosphereis recommended. The reflow temperature depends on the

Fig. 13. Shear force versus time of exposure to 125�C (150�C withAuSn80/20 solder).

Fig. 14. Flip chip assembly process flow chart of stencil printing of solderpaste on substrates or wafers with Ni/Au bumps.

applied pastes. After the reflow process and electrical testingan underfill was applied (Hysol 4511). For the experimentswe used an Asymtec (A612G) equipment for dispensing theunderfill material.

For the flip chip assembly solder printing only on waferswas performed. No additional paste was printed on the sub-strate. Test dies with 2.5 2.5, 5.0 5.0, 7.5 7.5, and 10.0

10.0 mm size and a pitch of 300m was used. Octagonalbond pads had 80m diameters. The dies had daisy-chainstructures for the measurement of transition resistances. Inaddition the three larger die types allowed four-point mea-surement of contact resistances. Ni/Au bumps with heights of5 m were chemically deposited on the wafers as UBM.

KLOESER et al.: FINE PITCH STENCIL PRINTING OF SN/PB AND LEAD FREE SOLDERS 47

TABLE VIJOINT HEIGHT ACHIEVED WITH DIFFERENT SOLDER PASTES

Alloy Joint height (�m) over substratemask

Bi/Sn-57/43 91�mSn/Pb-63/37 117�mSn/Bi/Cu-90/9.5/0.5 131�mSn/Ag-96.5/3.5 86�mSn/Cu-97/3 120�mAu/Sn-80/20 91�m

Fig. 15. Cross section of flip chip joints on FR-4 boards.

A thick film metallization of 8–10 m Pd/Ag and Au wasprocessed on the ceramic substrates. The FR-4 boards had20 m Cu leads and a final metallization of 4m Ni/Au. Thethickness of the solder mask was approx. 18m.

Fig. 15 shows an underfilled flip chip assembly on FR-4 boards. For this Sn/Pb paste was printed on a wafer andreflowed. Finally the bumped dies were assembled to the boardby a second reflow.

The AuSn80/20 metallurgy being a high temperature solder,could be used only on the LTCC ceramics. To allow a com-parison to a reference sample, SnPb63/37 and SnAg96.5/3.5solder was also used on the LTCC ceramics.

After joining and underfilling, samples of the different alloyswere cross sectioned and measured for the respective jointheight. In all cases a nearly void free underfill could beobserved as the underfill could easily penetrate the resultinggap between solder mask and chip. The joint heights reflect thedifferent bump volumes achieved by the printing the differentpastes. Table VI summarizes the results.

Figs. 16–19 show some representative cross sections fromflip chip assemblies.

Following the underfill cure, the samples were electricallytested for their initial contact resistance and integrity of thedaisy chained contacts. Subsequently they were subjected tothermal shock testing (55 C 125 C, 10 min dwell).Based on previous results, additional electrical tests were

(a) (b)

Fig. 16. Flip chip contacts of FR-4 boards; Sn/Pb-63/37.

(a) (b)

Fig. 17. Flip chip contacts of FR-4 boards: (a) Bi/Sn-53/47 and (b)Sn/Bi/Cu-90/9.5/0.5.

(a) (b)

Fig. 18. Flip chip contacts of FR-4 boards: (a) Sn/Ag-96.5/3.5 and (b)Sn/Cu-97/3.

(a) (b)

Fig. 19. Flip chip contacts ceramic: (a) Sn/Ag-96.5/3.5 and (b) Au/Sn-80/20.

performed after 500 and 1000 thermal shocks. Future investi-gations will extend this to more then 4000 cycles. The results

48 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING, AND MANUFACTURING TECHNOLOGY—PART C, VOL. 21, NO. 1, JANUARY 1998

Fig. 20. SnPb63/37 solder on FR-4 boards.

Fig. 21. SnBiCu90/9.5/0.5 solder on FR-4 boards.

Fig. 22. SnAg96.5/3.5 solder on FR-4 boards.

up to now are presented in Figs. 20–27 for the different solderalloys and substrate materials. The measurement of the contactresistance was performed by four point method. The 10 mm10 mm chips has 120 bumps and 16 of them are used formeasuring the contact resistance (7.5 mm7.5 mm; 84; 12/5mm 5 mm; 54; 8). For the experiments 12 chips of everytype were used.

So far, none of the used metallurgies show a significant risein contact resistance. (The increase observed with the smallestdie of the SnPb63/37 solder sample is expected to be due toan underfill void, as only one contact contributes to this raise.The sample with the SnAg96.5/3.5 metallurgy entered the testlate, therefore the results are not yet conclusive.

Fig. 23. BiSn53/47 solder on FR-4 boards.

Fig. 24. SnCu97/3 solder on FR-4 boards.

Fig. 25. SnPb63/37 solder on LTCC ceramics.

VII. CONCLUSION

A chemical wafer bumping process based on electrolessNi plating was presented. A very good uniformity of bumpshas been obtained and the results of reliability investigationswere excellent. Cost for chemical Ni bumping are significantlylower compared to other conventional techniques.

In the case of using Ni/Au bumps for flip chip assemblywafers, chips or substrates must be prepared by deposition ofsolder in a separate process. Therefore at the IZM differentpromising methods exist. The resulting flip chip assemblytechniques are very flexible and cost effective.

KLOESER et al.: FINE PITCH STENCIL PRINTING OF SN/PB AND LEAD FREE SOLDERS 49

Fig. 26. AuSn80/20 solder on LTCC ceramics.

Fig. 27. SnAg96.5/3.5 solder on LTCC ceramics.

Different lead free solder paste have been stencil printed onwafers, ceramics and FR-4 substrates. Different types of testdies with chemically plated Ni/Au bumps were soldered ina reflow furnace to the substrate. After underfilling the chipstheir reliability has been tested.

The results show that the combination of chemical bumpingand solder paste printing for flip chip assembly is very flexibleand a reliable low cost technique. Further investigation on thelead free solder pastes is necessary to find out the optimalmetallurgy for industrial application. A main issue to be solvedby the paste suppliers is to improve the printability of thesepromising alloys for flip chip applications.

In order to demonstrate the low cost approach of the flip chiptechnique presented in this paper a fully automatic flip chipline was established at IZM-Berlin. For industrial partners thiscenter will serve as a source for production of demonstratorsand prototypes as well as small and medium series.

ACKNOWLEDGMENT

The authors wish to thank B. Otto for electrical mea-surements, E. Busse for metallographic preparations, and M.Vogelsang and D. Wojakowski for their help. Special thanksgoes to Dr. Dietz, Degussa, Germany, for his support andhelpful discussions.

REFERENCES

[1] E. J. Vardaman, “International activity in flip chip on board technology,”in Proc. Nepcon West Conf., Anaheim, CA, Feb. 1995.

[2] K. Wong, K. Chi, and A. Rangappan, “Application of electroless Niplating in the semiconductor microcircuit industry,”Plat. Surf. Finish.,pp. 70–76, July 1988.

[3] K. Yamakawa, M. Inaba, and N. Iwase, “Maskless bumping by elec-troless plating for high pin count, thin and low cost microcircuits,” inProc. ISHM, Baltimore, MD, 1989, pp. 620–626.

[4] J. Simon, E. Zakel, and H. Reichl, “Electroless deposition of bumps forTAB technology,”Metal Finish., pp. 23–26, Oct. 1990.

[5] A. Ostmann, J. Simon, and H. Reichl, “The pre-treatment of Al bondpadsfor electroless nickel bumping,” inProc. IEEE MCM Conf., Santa Cruz,CA, 1993, pp. 74–78.

[6] A. Aintila, A. Bj orklof, E. Jarvinen, and S. Lalu, “Electroless Ni/Aubumps for flipchip-on-flex and TAB applications,” inProc. IEEE Int.Electron. Manufact. Technol. Symp., 1994, pp. 160–163.

[7] J. Audet, L. Belanger, G. Brouillette, D. Danovitch, and V. Oberson,“Low cost bumping process for flip chip,” inProc. ITAB Symp., SanJose, CA, 1995, pp. 16–21.

[8] M. Meehanet al., “High volume flip chip applications,” inProc. AreaArray Packag. Technol., Berlin, Germany, Nov. 1995.

[9] J. Giesler, S. Machuga, G. O’Malley, and M. Williams, “Reliability offlip chip on board assemblies,”ITAP Flip Chip Proc., San Jose, CA,1994, p. 127.

[10] H. Lowe, “No-clean flip chip attach process,”ITAP Flip Chip Proc.,San Jose, CA, 1994, p. 17.

[11] D. Suryanarayana, R. Hasiao, T. P. Gall, and J. M. McCreary, “Enhance-ment of flip-chip fatique life by encapsulation,”IEEE Trans. Comp.,Hybrids, Manufact. Technol., vol. 14, Mar. 1991.

[12] J. Lau, T. Krulevitch, W. Schar, M. Heydinger, S. Erasmus, and J.Gleason, “Experimental and analytical studies of encapsulated flip chipsolder bumps on surface laminar circuit boards,” inProc. Nepcon WestConf., Anaheim, CA, Feb. 1993.

[13] J. Kloeser, E. Zakel, F. Bechtold, and H. Reichl, “Reliability inves-tigations of fluxless flip chip interconnections on green tape ceramicsubstrates,” inProc. 45th Electron. Comp. Technol. Conf., Las Vegas,NV, May 1995, p. 1179.

[14] J. Kloeser, A. Ostmann, J. Gwiasda, F. Bechtold, E. Zakel, and H.Reichl, “Low cost flip chip technologies based on chemical nickelbumping and solder printing,” inProc. 29th Int. Symp. Microelectron.(ISHM), Mineapolis, MN, Oct. 1996.

[15] M. McCormack and S. Jin, “The design and properties of new, Pb-freesolder alloys,” inProc. IEEE/CPMT Int. Electron. Manufact. Technol.Symp., 1994.

[16] G. Motulla, K. Heinricht, A. Ostmann, and E. Zakel, “A low costbumping service based on electroless nickel and solder printing,” tobe ITAB’97 Conf., Sunnyvale, Ca, 1997.

[17] A. Ostmann, J. Kloeser, E. Zakel, and H. Reichl, “A low cost bumpingtechnology using electroless nickel/gold,” inProc. ITAB Symp., San Jose,CA, 1995.

[18] SMT-Magazine, p. 29, Jan./Feb. 1996.[19] M. McCormacket al., “New lead-free, Sn-Zn solder alloys,”J. Electron.

Mater., vol. 23, 1994.[20] J. Glazer, “Microstructure and mechanical properties of Pb-free solder

alloys for low cost electronic assembly,”Rev. J. Electron. Mater., vol.23, no. 8, 1994.

[21] N.-C. Leeet al., A Novel Lead Free Solder for the Electronics Industy.to be published.

[22] I. E. Anderson, “Tin silver copper: A lead free solder for broadapplications,” inProc. Nepcon W. Conf., Anaheim, CA, 1996.

[23] B. R. Alllenby et al., “An assessment of the use of lead in electronics,”Circuit World, vol. 19, no. 3, 1993.

[24] Dietz, Degussa, Germany.

Joachim Kloeser (M’95) received the M.S. degree in electrical engineeringfrom the Technical University of Berlin, Berlin, Germany, in 1991.

In 1992, he joined the Microperipheric Technologies Centre, where heworked on the development of flip chip bonding technologies with thickfilm ceramic substrates, focusing electric testing and reliability of flip chipinterconnections. Since July 1993, he has also worked in a specializedgroup on chip interconnection and reliability with the special regard to lowcost flip chip technologies. In 1996, he became the group leader of flipchip technologies at the Department of reliability of chip interconnectiontechnology and multichip modules, IZM, Berlin. He is the author of severalpublications on flip chip bonding techniques and reliability.

50 IEEE TRANSACTIONS ON COMPONENTS, PACKAGING, AND MANUFACTURING TECHNOLOGY—PART C, VOL. 21, NO. 1, JANUARY 1998

Katrin Heinricht studied process engineering at theTechnische Fachhochschule Berlin (TFH), Berlin,Germany, with the specialization on thermal processengineering.

For one year she was with Pac Tech GmbH,where she had developed the ultra fine pitch stencilprinting on wafers, and was responsible for theimplementation of flip chip processes. Since August1997, she has worked at the Fraunhofer Institut,IZM, Berlin. While there, she has transferred theprinting process from the development stage to

production machines. She is responsible for investigations and services ofstencil printing and is supporting the flip chip and CSP Demonstration center.

Kai Kutzner received the diploma in mechanicalengineering from the Technische Fachhochschule,Berlin, Germany, in 1996.

He joined the Chip Interconnection and Re-liability Department, Fraunhofer Institut f¨urZuverlassigkeit und Mikrointegration, Berlin, in1996. He is currently working on the field of fullyautomatically flip chip processes.

Erik Jung received the B.S. degree in physics andtheoretical informatics and the diploma in physicsand physical chemistry, both from the University ofKaiserslautern, Kaiserslautern, Germany, in 1992and 1994, respectively.

He joined the Chip Interconnection and Re-liability Department, Fraunhofer Institut furZuverlassigkeit und Mikrointegration, Berlin, in1994. He is currently working on the field of chipbumping, flip chip interconnection, and advancedpackaging technologies.

Andreas Ostmann reived the Diploma in appliedsemiconductor physics from the Technical Univer-sity of Berlin, Berlin, Germany, in 1991.

Since 1992, he has been with the MicroperiphericResearch Centre, Technical University of Berlin. Hedeveloped the electroless bumping technology ofIZM Fraunhofer Institute. Currently he is managinga flip chip assembly project and coordinates the lowcost bumping activities of the instute.

Herbert Reichl (M’89–SM’97) was a Junior Scientist at the FraunhoferIFT, Berlin, Germany, from 1971 to 1977 and the Head of the Sensor andSemiconductor Department from 1977 to 1987. He was Full Professor atFH Munich, Germany, from 1981 to 1987. He has been a Full Professorat the Microelectronics Department, Technical University of Berlin, since1987 and Head of Institute for the Fraunhofer Institute for Reliability andMicrointegration IZM since 1993. He is the editor of numerous publications.He has also written and co-authored many books and more than 400 articles.

Dr. Reichl received an honorary doctorate from the faculty of ElectricalEngineering and Information Technology, Technical University of Chemnitz,Chemnitz, Germany, in November 1995. At the International Flip Chip,Ball Grid Array, TAB and Advanced Packaging Symposium (ITAP’95), hewas presented with the Special Award of the Semiconductor TechnologyCenter. He is a distinguished Senior Member of the International Societyfor Hybrid Microelectronics (ISHM). Furthermore, he is Member of theAdvisory Board of the European Liaison Office of the German ScientificResearch Organizations (KOWI), of the German Microelectronics Societyand the German Association of Engineers (VDI/VDE). He is the chairmanof the Organizing Committee of the SMT/ES&S/Hybrid, of the Micro SystemTechnologies Conference and of the European Conference on ElectronicPackaging Technology (EuPac). In 1996, he was elected head of the Boardof Directors of the Fraunhofer Group Microelectronics, the council of sevenFraunhofer Institutes working in the area of microelectronics.